The present invention relates to an electroplating technique and, more particularly, to a plating method and plating apparatus for a semiconductor device.
In recent years, copper has received a great deal of attention as an interconnection material in order to reduce the interconnection resistance of an LSI and improve its reliability. The copper interconnection forming methods include CVD, sputter reflow, and plating. Of these methods, plating is simple in process and low in cost, exhibits high filling performance, and can form a high-performance interconnection.
However, currently available plating apparatuses do not satisfactorily consider a semiconductor device manufacturing process. The conventional apparatus basically adopts a “plating bath” method following the plating industry. According to this method, a semiconductor substrate is plated by dipping it in a plating bath or cup filled with a plating solution.
This classical plating method has not achieved progression particularly considering the semiconductor device manufacturing process. Thus, when the method is applied to the semiconductor device manufacturing process, the following serious problems arise.
(1) It is difficult to perform precise control of an absolute film thickness in nanometers that is much smaller than the film thickness in a general plating industry, and to ensure high uniformity on the substrate surface.
(2) Bubbles and dust greatly influence the semiconductor process to which a very low defect density on a fine pattern is demanded.
(3) A voltage/current from a cathode can only be applied from the periphery of a substrate outside a region where a pattern is formed. If the electrode is brought into contact with the inside of the substrate where the pattern is formed, scratches or dust is generated to decrease the product yield. This is disadvantageous in a situation in which the wafer size in the semiconductor process is increasing year by year. That is, the conductive layer of an electroplating solution must be made thick on the wafer surface. Otherwise, the resistance from the cathode potential supply portion at the periphery of the substrate to the center of the substrate increases, failing to ensure the plating current at the center. However, the thickness of the conductive layer is limited by process constraints.
(4) It is difficult to perform locally plating in accordance with a regular pattern formed on a semiconductor substrate. It is also difficult to perform positive control of the film thickness on the surface of a semiconductor substrate (wafer), for example, to make the periphery thick in accordance with requirements in a post-plating step (e.g., CMP). If the plating solution is not wanted to attach to the lower surface of the substrate in order to prevent contamination of the substrate or the like, a special seal must be used to protect the lower surface.
(5) In forming a film into a three-dimensional pattern, film formation on projections cannot be suppressed. An example of the most typical applications of a plating metal film among semiconductor processes is formation of a metal film for forming a damascene interconnection. In the damascene process, a plating metal is buried in an interconnection groove or hole, and a metal film formed outside the groove or hole is removed by CMP or the like. Considering load reduction in a subsequent CMP step or the like, formation of the plating film on a portion except for the groove or hole must be prevented as much as possible. The above-described requirements and problems unique to the semiconductor process obstruct the use of plating.